1. Field of the Invention
The present invention relates to an encode system, an encode method, a decode system, a decode method, an encode data recording device, an encode data recording method, an encode data transmitting device, an encode data transmitting method and a recording medium which are suitably used when audio data or video data are digitalized and packeted according to an MPEG (Moving Picture Experts Group) system, and these data are transmitted through a prescribed network and received at a reception side.
2. Description of Related Art
FIG. 15 shows the construction of a conventional data transmission system.
An encoder 1 encodes video signals and audio signals according to an MPEG-2 system, for example, and inputs these data to a system encoder 2. The system encoder 2 packets the input video signals and the audio signals, and also adds time stamps to these data to transmit the data onto a network 3. The network 3 is an ATM (Asynchronous Transfer Mode) network, for example, and a statistical multiplexing processing is conducted. That is, when data of a packet are transmitted, data of another packet are held in a buffer memory. When the transmission of the data of the packet concerned is completed, the data of the other packet (cells) are read out from the buffer memory and a transmission processing is executed on many nodes constituting the network 3.
The data which are transmitted through the network 3 are input to a system decode 4. For example, as shown in FIG. 16, the system decoder 4 is constructed by a time stamp take-out circuit 11, a PLL circuit 12 and a system decoder 13. The system decoder 13 releases the packetting of the input packeted audio data and the video data, and outputs the obtained audio stream and the video stream to the decoder 5.
On the other hand, the time stamp take-out circuit 11 takes out a time stamp contained in the input data, and outputs it to the PLL circuit 12. The PLL circuit 12 generates a system clock by using the input time stamp, and outputs the system clock to the decoder 5. In the case of the MPEG-2 system, the frequency of the system clock is set to 27 MHz.
The decoder 5 decodes the streams of the audio data and the video data supplied from the system decoder 13 on the basis of the system clock input from the PLL circuit 12.
The PLL circuit 12 is constructed as shown in FIG. 17, for example. The time stamp which is extracted by the time stamp take-out circuit 11 is input to a subtracter 21. The time stamp is set as PCR (Program Clock Reference) in the transport stream of the MPEG-2 system. The transport stream is set as a fixed packet of 188 bytes, and it is transmitted as a stream of a fixed speed. PCR is transmitted at an interval within at least 0.1 second. In the case of transmission, it is disposed at the header of a packet.
PCR represents the timing of an encode in the encoder 1 by a count value of the system clock of the system encoder 2. The subtracter 21 calculates the difference between the PCR and the count value of the system clock of the counter 24 (system clock in the system decoder 4). The output of the subtracter 21 is input to a low-pass filter (LPF) 22 and smoothed, and then input to a DA (Digital/Analog) converter and VCO (voltage control oscillator) 23. The DA converter and VCO 23 converts the digital signal input from the low-pass filter 22 to the analog signal, and uses the analog signal as a control voltage to produce a system clock whose frequency corresponds to the control voltage.
The system clock is supplied to the decoder 5, and also input to the counter 24 to be counted. The count value of the counter 24 is supplied to the subtracter 21 as a signal representing the frequency and phase of the system clock at that time.
When the data encoded at the transmission side are transmitted through the network 3 to the reception side and then decoded at the reception side as described above, the system clock of the decoder side could be easily synchronized with the system clock of the encoder side if the time stamps arrive at the decoder side at the accurately same interval.
However, there actually occurs delay fluctuation on the network 3. That is, the network 3 carries out the statistical multiplexing processing on the data every packet, and in order to transmit a prescribed packet and another packet onto one transmission path, one packet is required to be stored in a buffer memory and kept on standby when the other packet is transmitted. When the transmission of one packet is completed, the transmission processing of the other packet which is kept on standby is performed. Since the processing as described above is carried out on many nodes (ATM switches) in the network 3, the transmitted packet (ATM cell) is caused to have random delay fluctuation. If the delay fluctuation is left as it is, it will be difficult to perform the accurate decoding operation at the decoder side.
Therefore, in order to cancel the random delay fluctuation, it is considered that the time stamps are rewritten into values which are in consideration of the delay fluctuation. However, this processing complicates the construction of the network 3.
Alternatively, it is considered that the random delay fluctuation in the network 3 is absorbed by a PLL circuit 12. However, since the delay fluctuation is extremely large, in order to absorb the random delay fluctuation, the PLL circuit 12 needs a long time to synchronize it or must be designed in a complicated circuit construction.
Furthermore, in the encoder 1, the encode processing is carried out at a variable bit rate. Therefore, data quantity increases for a complicated image, and it is reduced for a simple image.
On the other hand, in the transport stream, the length of the packet is set to a constant value of 188 bytes. Therefore, when data quantity is large, the arrival interval of packets is short. When the data quantity is small, the arrival interval of packets is long. That is, the data rate at which the packet is transmitted is varied in accordance with the code quantity produced in the encoder 1.
When the variation of the arrival interval and the delay fluctuation as described above are left as they are, it would be difficult to perform the accurate decoding operation at the decoder side.
The above problem also occurs when the data output from the system encoder 2 are not directly transmitted, but temporarily stored in a recording medium and then transmitted,